1. Field of the Invention
The present invention relates to integrated circuit fabrication processes and integrated circuit substrate structures, and more particularly, to a layer structure providing a shielding effect on near-end electromagnetic interference (EMI) and distal-end EMI between through silicon vias, applicable in the integrated circuit fabrication processes.
2. Description of Related Art
As various portable electronic devices and peripheral products thereof used in communication, network and computer fields have been made more and more compact in size, semiconductor fabrication processes are continuously being improved in its degree of integration, and high-density package structures become a target in response to those electronic devices getting to have more functions and higher performance. Thus, there is being developed three-dimensional (3D) packaging technology for fabricating semiconductor packages, so as to provide a high-density package system suitable for the more compact and better-performance electronic devices.
The 3D packaging technology involves a 3D integrated circuit, allowing a plurality of layers of chips or circuit substrates (including active components) to be integrated by various ways onto a single integrated circuit. More specifically, by the 3D integrated circuit technique, a plurality of chips are integrally mounted on a single integrated circuit in a stereoscopic or 3D manner. Accordingly, the 3D integrated circuit technique requires high-density electrical interconnections for providing electrical contacts on active surfaces and/or back surfaces of the chips in order to achieve the 3D stacking and/or high-density package structure.
Through Silicon Via (TSV) technology is a critical technique used in fabricating the 3D integrated circuit. By forming through silicon vias in the chips or substrate to provide vertical electrical connections, more chips can be stacked on a predetermined area of the integrated circuit and thereby the stacking density is enhanced. Moreover, a good TSV design may effectively integrate different processes or reduce transmission delay, and the use of shorter interconnections reduces power consumption, improves performance and increases transmission bandwidth. Thus, the TSV technology allows the chip-stacking package structure to be further made with low power, high density and miniaturization processes.
FIG. 1 illustrates a silicon substrate 100 having conventional TSV structures. As shown in FIG. 1, the silicon substrate 100 is formed with two through silicon vias 102, 104 between which there is no electromagnetic interference (EMI) shielding structure provided.
However, with the number of through silicon vias of the chip being increased and a pitch between the adjacent through silicon vias becoming smaller, a certain degree of EMI effect may be generated between the plurality of through silicon vias, thereby adversely affecting the overall performance of the chip.
FIG. 2 illustrates a simulation result showing a distal-end EMI effect generated between the through silicon vias 102, 104. As shown in FIG. 2, the distal-end EMI (curve S31T) between the through silicon vias 102, 104 is −47.883 dB under the condition of signal frequency being 10 GHz, and is −67.897 dB under the condition of signal frequency being 1 GHz. Moreover, FIG. 3 illustrates a simulation result showing a near-end EMI effect generated between the through silicon vias 102, 104. As shown in FIG. 3, the near-end EMI (curve S41T) between the through silicon vias 102, 104 is −45.448 dB under the condition of signal frequency being 10 GHz, and is −65.168 dB under the condition of signal frequency being 1 GHz.
Therefore, how to provide a layer structure applicable in a 3D integrated circuit system and capable of diminishing the influence caused by an EMI effect between a plurality of through silicon vias in order to overcome the above drawbacks of the conventional technology, is becoming one of the most popular issues in the art.